CVPR 2020
Learned Image Compression with GMM and Attention
We proposed a learned image compression model incorporating a Gaussian mixture model and attention mechanisms, achieving state-of-the-art performance in 2020.
SUN Lab
Yokohama National University
Research Details
Research Details
Detailed descriptions of SUN Lab research topics.
Learned Image Compression
Traditional image compression standards have been developed over more than 30 years. In contrast, learned image compression has demonstrated superior coding performance with neural networks.
CVPR 2023 Highlight
Learned Image Compression with Mixed Transformer-CNN Architectures
We proposed a framework that combines Transformer and CNN architectures for high-efficiency learned image compression.
Learned Video Compression
Learned video compression has demonstrated superior coding efficiency compared with traditional video compression standards.
ICML 2026
MoVie: Multimodal Video Compression with Text Guidance
MoVie is a text-guided multimodal video compression framework that combines video-centric Transformer-CNN blocks, dual-stage text fusion, and history-conditioned coding.
CVPR 2025
Learned Video Compression with Feature-Level Attention
We proposed a learned video compression network using feature-level attention to improve coding efficiency.
Image Coding for Machines
Image coding for machines aims to improve the accuracy of machine vision tasks, such as object detection and tracking, while reducing transmission cost.
PCS 2022
Semantic Segmentation in Learned Compressed Domain
We studied semantic analysis directly in the learned compressed domain to support efficient machine-oriented visual coding.
FPGA-Based LIC Systems
FPGAs provide flexibility, reconfigurability, and high power efficiency. We developed FPGA-based neural engines and applied them to real-time learned image compression systems.
Real-Time Learned Image Codec on FPGA
The demo system captures 720p 30 fps video, encodes it on a Xilinx VCU118 FPGA board, decodes it on another FPGA board, evaluates latency and power, and verifies cross-platform operation.
ASIC Chip Design
ISSCC 2016
8K HEVC Decoder Chip
We developed an 8K 120 fps HEVC decoder chip. I was responsible for the inverse transform and dequantization modules.
